The technology described in this disclosure relates generally to integrated circuits and more particularly to integrated circuit design.
A defect is an error caused in a circuit during a manufacturing process. A fault model is a mathematical description of how a defect alters circuit design behavior. For example, in a stuck-at fault model, a signal (e.g., a gate output) is stuck at a 0 or 1 value, independent of the inputs to the circuit. The logic values observed at primary outputs of a circuit, while applying a test pattern (e.g., a sequence of input signals) to some devices under test (DUT), are called the output of that test pattern. The output of a test pattern, when testing a fault-free circuit that works exactly as designed, is called the expected output of that test pattern. A fault is detected by a test pattern if the output of that test pattern, when testing a circuit that has only that one fault, is different than the expected output.
Automatic Test Pattern Generation (ATPG) includes an electronic design automation method/technology used to find a test pattern that, when applied to a circuit, enables automatic test equipment to distinguish between correct circuit behavior and faulty circuit behavior caused by defects. For example, the generated test patterns are used to test manufactured circuits, and in some cases to assist with failure analysis. The effectiveness of ATPG is measured by the amount of modeled defects, or fault models, that are detected and the number of generated test patterns. These metrics generally indicate test quality (e.g., higher with more fault detections) and test application time (e.g., higher with more test patterns). The ATPG efficiency is usually influenced by the fault model under consideration, the type of circuit under test (e.g., full scan, synchronous sequential, or asynchronous sequential), the level of abstraction used to represent the circuit under test (e.g., gate, register-transfer, switch), and the required test quality.
The ATPG process for a targeted fault includes two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault model site that is opposite of the value produced by the fault model. Fault propagation moves the resulting signal value, or fault effect, forward by sensitizing a path from the fault site to a primary output. If a fault is intrinsically undetectable, no test patterns may exist to detect that particular fault. For example, a redundant circuit is designed to avoid output changes caused by a single fault, and thus a single fault in the circuit may be inherently undetectable.
Design for testing (DFT) represents a circuit design technique that adds certain testability features to a circuit design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed circuit. The purpose of manufacturing tests is to validate that the circuit contains no manufacturing defects that could adversely affect the circuit's correct functioning. DFT plays an important role in the development of test programs and as an interface for test application and diagnostics. ATPG is much easier if appropriate DFT rules and suggestions have been implemented.